Generally, electrostatic discharge (ESD) networks comprise, among other things, an ESD current path, control circuits (e.g., switches, floating well circuits, and/or pull-up gate circuits), and/or a self-protection pull-down device (e.g., designed to mitigate leakage current). For example, a snapback NMOS may be used as a pull down device and/or an ESD current path within an ESD network. However, a snapback NMOS device generally requires an extended drain region such that gate to gate spacing of the snapback NMOS is larger than desired (e.g., greater than one micro-meter), for example. Larger gate to gate spacing generally occupies a greater amount of space on a device, which may be undesirable (e.g., at least because model accuracy may be reduced and/or fewer transistors may be fabricated on a die and/or device, for example). Additionally, parasitic resistances associated with the extended drain region may be introduced (e.g., and/or undesirable). Moreover, snapback NMOS devices are generally more difficult to fabricate (e.g., by comparison with non-snapback NMOS devices), for example. That is, for example, drain extension, resist protective oxide (RPO), and/or additional implanting (e.g., epitaxial) may be required to fabricate a snapback NMOS. Furthermore, layout styles associated with drain extension generally degrades process yield, thus requiring a special process to fabricate the snapback NMOS accordingly.